----------------------------------------------------------------------------------
-- INSTITUTION:    Xidian University
-- DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
-- 
-- Create Date:    16:53:58 02-14-2016 
-- Design Name:    PWM_COMPARATOR 
-- Module Name:    PWM_COMPARATOR
-- Project Name:   PWM
-- Target Devices: EP3C16F484C6
-- Tool versions:  Quartus II 13.1
-- Design Lauguage:VHDL
-- Dependencies:   -
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: DE0 Board Input Freguency = 50 MHz
--                      Destiny Output  Freguency =  1 Hz
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity PWM_COMPARATOR is
	port(
		i_compare_value: in STD_LOGIC_VECTOR (6 downto 0);      --输入
		i_compare_set_value: in STD_LOGIC_VECTOR (6 downto 0);  --输入。这两个输入端口输入的信号进行比较
		o_compare_result: out STD_LOGIC
	);
end entity PWM_COMPARATOR;

architecture behavior of PWM_COMPARATOR is
begin
	process(i_compare_value,i_compare_set_value)	           --通过占空比来调节灯的亮度，e.g计数计到10就是占空比10%，
		begin
			if (i_compare_value < i_compare_set_value) then	  --要是i_compare_value < i_compare_set_value，比较结果就输出
				o_compare_result <='1';                --1就是小灯亮
			else
				o_compare_result <='0';
			end if;
	end process;
end architecture behavior;
